More register changes in a scanline

Using standard techniques to load custom regs via COPPER we can load. There are other DMA channels which we could use to change as much register values as possible.

From AGAManual we learn that "All COPPER instructions require 2 bus cycles (and two instruction words). Since only the odd bus cycles are requested, 4 memory cycle times are required per instruction." As one chip-memory cycle takes 280 ns, beam will display 2 LoRes pixels during that period. We also find out that "It has priority over the blitter and micro." And it looks like it has lower priority than bitplane and probably sprite DMA as these are stealing cycles when there's more than 4 bitplanes used. So if we use up to 4 bpl's, we can have about 56 color register changes (448 pixels per scanline/2 pixel per cycle/4 cycles per instrucion.)

However there's a way to nearly double this result. Since Copper uses odd and CPU uses even bus cycles to access memory, it is possible to load twice as much custom registers, using both of them simultanously.