DMACON

         This register controls all of the DMA channels, and contains
         blitter DMA status bits.


         +------+----------+--------------------------------------------+
         | BIT# | FUNCTION | DESCRIPTION                                |
         +------+----------+--------------------------------------------+
         | 15   | SET/CLR  | Set/Clear control bit. Determines if bits  |
         |      |          | written wit a 1 get set or cleared.        |
         |      |          | Bits written with a zero are unchanged.    |
         | 14   | BBUSY    | Blitter busy status bit (read only)        |
         | 13   | BZERO    | Blitter logic zero status bit. (read only) |
         | 12   | X        |                                            |
         | 11   | X        |                                            |
         | 10   | BLTPRI   | Blitter DMA priority (over CPU micro)      |
         |      |          | (also called "blitter nasty")              |
         |      |          | (disables /BLS pin, preventing micro       |
         |      |          | from stealing any bus cycles while         |
         |      |          | blitter DMA is running)                    |
         | 09   | DMAEN    | Enable all DMA below (also UHRES DMA)      |
         | 08   | BPLEN    | Bit plane DMA enable (BPLxPT)             |
         | 07   | COPEN    | Coprocessor DMA enable (COPxLC)           |
         | 06   | BLTEN    | Blitter DMA enable (BLTxPT)               |
         | 05   | SPREN    | Sprite DMA enable (SPRxPT)                |
         | 04   | DSKEN    | Disk DMA enable (DSKPT)                   |
         | 03   | AUD3EN   | Audio chanel 3 DMA enable (AUD3LC)        |
         | 02   | AUD2EN   | Audio chanel 2 DMA enable (AUD2LC)        |
         | 01   | AUD1EN   | Audio chanel 1 DMA enable (AUD1LC)        |
         | 00   | AUD0EN   | Audio chanel 0 DMA enable (AUD0LC)        |
         +------+----------+--------------------------------------------+


         Note:  Because of timing problems with '020+
         processors and/or old chip-sets, you should wait a
         short while before testing BBUSY.  A "tst.w DMACONR"
         before the test will provide the appropriate delay.