MoreInts

         The Amiga's hardware is capable of generating 14
         interrupts on seven levels.  Level 1-6 are maskable,
         and level 7 is an NMI.  This register tells you
         which ints are enabled or disabled.  To enable or
         disable an interrupt, use this register's write
         address, INTENA ($dff09a).  To force an interrupt to
         take place, use register INTREQ ($dff09c).  To
         actually find out what type of interrupt is taking
         place, read INTREQR at $dff01e.


         When the uP receives an interrupt signal, it takes
         the level number, multiplies it by two, and adds
         $fffff1 to the result.  This calculation produces
         the address of a byte long memory offset contained
         in ROM.  The memory offset is then multiplied by
         four to obtain the address of the interrupt's auto
         vector - a location that contains the pointer to the
         corresponding interrupt processing routine.  Under
         the current version of ROM, these four byte pointers
         are stored in locations $64, $68, $6c, $70, $74,
         $78, and $7c, for the level 1-7 interrupts
         respectively. Note though that addresses may be
         modified by changing VBR register.


         To prioritize interrupts that share the same level
         number, Exec has assigned each interrupt a pseudo
         priority number.  Again, the higher this number, the
         higher the priority:


      +-------------------------+-------------+-----------------+
      | Interrupt               | 680x0 Level | Pseudo-Priority |
      +-------------------------+-------------+-----------------+
      | Software                |      1      |        1        |
      | Disk Block Done         |      1      |        2        |
      | Transmit Buffer Empty   |      1      |        3        |
      | CIA-A (exp bus pin 19)  |      2      |        4        |
      | Copper                  |      3      |        5        |
      | Vertical Blank          |      3      |        6        |
      | Blitter Done            |      3      |        7        |
      | Audio Channel 2         |      4      |        8        |
      | Audio Channel 0         |      4      |        9        |
      | Audio Channel 3         |      4      |       10        |
      | Audio Channel 1         |      4      |       11        |
      | Read Buffer Full        |      5      |       12        |
      | Disk Sync Pattern Found |      5      |       13        |
      | CIA-B (exp bus pin 22)  |      6      |       14        |
      | NMI                     |      7      |       15        |
      +-------------------------+-------------+-----------------+


         If you plan on handling interrupts completely on
         your own, note that interrupt processing routines
         are always executed in SUPERVISOR mode.  As a
         minimum, your routine should clear the corresponding
         bit in the INTREQ register to clear that interrupt.
         Use the 680x0 instruction RTE to return from an
         interrupt.


         To cause a raster interrupt to occur, simply make
         the copper wait for the desired line, then store
         #$8010 in INTREQ:


                  wait 0,100            ; wait for line 100
                  move #$8010,INTREQ    ; trigger interrupt